Switch-level timing simulation based on two-connected components
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United States of America Patent
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Apr 19, 1994
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N/A
app pub date -
Sep 6, 1991
filing date -
Sep 6, 1991
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Abstract
A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.
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