Computer connection circuit in facsimile
Number of patents in Portfolio can not be more than 2000
United States of America Patent
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Apr 12, 1994
Grant Date -
N/A
app pub date -
Nov 21, 1991
filing date -
Nov 28, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The invention provides a computer connection circuit in a facsimile, comprising: control and memory unit including CPU(Central Processing Unit)(11a), RAM(Random Access Memory)(11c), and ROM(Read Only Memory)(11b) for controlling a general operation control of the facsimile; address decoder 12 connected to the control and memory unit through an address bus, for selecting and enabling an output terminal according to an input address; a modem 31 connected to the control and memory unit through a date bus and connected to communication lines, in which is driven by a first chip selection signal of the address decoder 12 and requires an interrupt to the control and memory unit in sending/receiving image information; and an UART51(Universal Asynchronous Receiver & Transmitter) connected to the control and memory unit and to RS232C interface means of the computer, in which requites an interrupt to the control and memory unit in sending/receiving image and character information to/from the computer and is driven by a second chip selection signal of the address decoding decoder 12.
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