Method and apparatus for deferred package assignment for components of an electronic circuit for a printed circuit board
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United States of America Patent
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Mar 22, 1994
Grant Date -
N/A
app pub date -
Jun 4, 1991
filing date -
Jun 4, 1991
priority date (Note) -
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Abstract
A computer aided design tool provides a user with the capability of generating a design implementation for electronic circuitry. In this system the user generates a design schematic specifying a functional description of a design for electronic circuitry without the need for specifying packaging information. The system is provided with a packaging tool for generating a physical package for the circuitry of the design schematic. Use of the packaging tool may be deferred until the design schematic has been completed and verified. Further, a user of the system has the option of specifying certain packaging information when creating the design schematic or delaying such specification until just prior to packaging of the design.
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