Method of manufacturing a semiconductor device having buried elements with electrical characteristic
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
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Feb 15, 1994
Grant Date -
N/A
app pub date -
May 8, 1992
filing date -
May 8, 1991
priority date (Note) -
In Force
status (Latency Note)
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Abstract
There are disclosed a semiconductor device having electrical elements buried a SOI substrate and a manufacturing method thereof, the manufacturing method of the invention comprising the steps of: (a) forming a first isolating insulator layer at a seed wafer by using an isolation mask, depositing a second isolating insulator layer overlying the first isolating insulator layer and the seed wafer, and defining contact holes by using a contact mask to form contacts on the seed wafer; (b) depositing a first polysilicon layer on the second isolating insulator layer and the contacts and doping an impurity into the first polysilicon layer; (c) patterning the first polysilicon layer to define an electrical element, depositing an insulating layer around the electrical element, and forming a second polysilicon layer overlying the second isolating insulator layer and the insulating layer; (d) doping an impurity into the second polysilicon layer for connecting with a handling wafer, and polishing the second polysilicon layer thus doped to form a mirror surface; (e) depositing an insulating layer for connection on the handling wafer, and performing a thermal process to bond the handling wafer and the mirror surface through the insulating layer for connection; and (f) polishing the seed wafer until the first isolating insulator layer as a polishing stopper is exposed, to form the SOI substrate having an active region where a device is formed, by the invention the efficiency of chip area can be promoted.
First Claim
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Family

- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
KOREA ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE | DAEJEON KOREA |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kang, Sang-Won | Daejeon, KR | 23 | 683 |
# of filed Patents : 23 Total Citations : 683 | |||
Kang, Won-Gu | Daejeon, KR | 5 | 740 |
# of filed Patents : 5 Total Citations : 740 | |||
Yu, Hyun-Kyu | Daejeon, KR | 146 | 3301 |
# of filed Patents : 146 Total Citations : 3301 |
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Patent Citation Ranking
- 260 Citation Count
- H01L Class
- 98.97 % this patent is cited more than
- 31 Age
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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