Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking
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United States of America Patent
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Jan 4, 1994
Issued Date -
N/A
app pub date -
Jul 20, 1990
filing date -
Apr 13, 1987
priority date (Note) -
Expired
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Abstract
Bus interfacing circuitry provides for high speed communication of signals on a bus by using circuitry that synchronizes data transfers to a single reference point, executes commands from a dual-ranked buffer in order to reduce time consumed by external interrupts, and stores multiple bytes in a FIFO buffer to allow rapid sequential transfers; while also providing a flexible input/output configuration allowing both single-ended and differential mode connections.
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