Flash-type nonvolatile semiconductor memory having precise erasing levels
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United States of America Patent
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Dec 28, 1993
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N/A
app pub date -
Apr 21, 1993
filing date -
Apr 22, 1992
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Abstract
A flash-type nonvolatile semiconductor memory having a precise erasing level is disclosed. The memory of the present invention includes a plurality of source lines arranged in parallel to bit lines in correspondence with columns of a cell matrix, a plurality of level judging circuits arranged at each bit line and a plurality of source line switches arranged at each source line. In an erasing operation, memory cells are erased so as to not generate over-erased cells, every selected memory cell is simultaneously tested whether or not it has a threshold less than a upper limit of an object range, and only unsufficiently erased memory cells are further erased in a re-erasing step by being controlled with the source line switches.
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