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Abstract

A dynamic detector normalization circuit for normalizing detector output data using detector-error-correcting offset and gain coefficients that are updated in real time. The offset/gain coefficients are computed by a coefficient processor (20) at selected update intervals based on detector responses to a reference source. The coefficient processor averages detector reference responses over a number of update intervals to obtain updated offset/gain coefficients with greater precision than that available from the detector network. The detector normalization circuit (10) includes offset addition logic (12) and gain coefficient logic (14) for reading-out the offset/gain coefficients stored in respective RAMs (13, 15). For each detector output sample received by the detector normalization circuit (10), an offset addition operation 40 adds to the sample the MS bits of the offset coefficient. After the addition operation, the LS bits of the offset coefficient (representing increased precision available from the offset coefficient) are concatenated, and after underflow/overflow protection (42), an offset-corrected detector sample is obtained. A gain multiplication operation (50) multiplies the offset-corrected detector sample by the gain coefficient to obtain an offset/gain-corrected detector sample. After discarding LS bits representing unnecessary precision, and range-clipping (60), the normalization circuit (10) outputs normalized detector data with the desired precision. The detector normalization technique is described in connection with an exemplary application for normalizing thermal detector array output in a thermal imaging system.

First Claim