Method of estimating logic cell delay time
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United States of America Patent
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Dec 28, 1993
Grant Date -
N/A
app pub date -
Dec 5, 1990
filing date -
Dec 5, 1990
priority date (Note) -
Expired
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Abstract
A method for approximating the delay time of an excitation through a logic cell using the summation of a base delay, which is a function of delay coefficients for the cell and the total output load capacitance of the cell, and a rise/fall time correction, which is determined from the output rise/fall time of the driving cell and the sensitivity of the analyzed cell to rise/fall time. Other corrections/compensating factors include a performance derating factor which accounts for the multiplicative effects of operating voltage, temperature and process.
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