Insulated gate semiconductor device
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United States of America Patent
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Dec 14, 1993
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N/A
app pub date -
Dec 10, 1992
filing date -
Dec 8, 1988
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Abstract
A MOS device comprising a parallel array of a plurality of unit structures on a substrate, each unit structure including a first semiconductor layer of a first conductivity type, an oxide layer disposed on a major surface of the first semiconductor layer, a control electrode formed on the oxide layer, and second and third semiconductor layers separated from each other by the first semiconductor layer. The electric current flowing through a surface layer in contact with the oxide layer is controlled by the voltage applied to the control electrode, and the oxide layer is relatively thick between the first semiconductor layer and the control electrode on the periphery of the unit structures located on the periphery of the substrate and relatively thin between the first semiconductor layer and control electrode in other regions of the MOS device.
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