Semiconductor array and method for its manufacture
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United States of America Patent
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Dec 7, 1993
Grant Date -
N/A
app pub date -
May 18, 1992
filing date -
Jun 26, 1991
priority date (Note) -
Expired
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Abstract
A semiconductor array in a CMOS technology is described in which the gate electrodes are of p.sup.+ -doped polysilicon in the case of p-channel transistors and of n.sup.+ -doped polysilicon in the case of n-channel transistors. If the gate electrodes of two complementary transistors are connected at the gate level, a polysilicon diode is created at the connection point. In accordance with the invention, the polysilicon diode is short-circuited with a polysilicide layer. A method is described for short-circuiting this polysilicon diode without additional masking steps using a metal silicide layer. In a further embodiment of the invention, the silicide is restricted to the area of the polysilicon diode. In addition, a method is described using which the polysilicon diodes can be short-circuited in a self-adjusting polysilicide process.
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