Semiconductor memory device and operating method thereof with transfer transistor used as a holding means
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United States of America Patent
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Nov 30, 1993
Grant Date -
N/A
app pub date -
Aug 31, 1989
filing date -
Aug 31, 1988
priority date (Note) -
Expired
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Abstract
A semiconductor memory device comprises a memory cell array (1) comprising a plurality of memory cells (MC) arranged in a matrix. A Y decoder (5) is responsive to an external address signal for outputting a selecting signal which simultaneously selects a plurality of columns in the memory cell array (1). The selecting signal is held by a latch transistor (LT). A selector (9b) sequentially applies input data to a plurality of columns simultaneously selected by the selecting signal held by the latch transistor (LT). During operation of the selector (9b), a binary counter (11) generates the subsequent internal column address signal, to which the Y decoder (5) is responsive for generating a selecting signal which simultaneously selects another plurality of columns in the memory cell array (1). As a result, the selecting operation in response to the subsequent selecting signal is performed immediately after operation of the selector (9b) is accomplished.
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