Packaging architecture for a highly parallel multiprocessor system

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United States of America Patent

PATENT NO 5251097
SERIAL NO

07536395

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Abstract

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The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.

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Patent Owner(s)

Patent OwnerAddress
SILICON GRAPHICS INTERNATIONAL CORP46600 LANDING PARKWAY FREMONT CA 94538

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Steve S Chippewa Falls, WI 21 2172
Girling, Dennis F Cadott, WI 2 106
Heid, Lisa Eau Claire, WI 1 106
Lesmerises, Felix R Eau Claire, WI 1 106
Massopust, Dan L Eau Claire, WI 5 163
Paffel, Douglas C Stanley, WI 2 146
Pautsch, Greg W Chippewa Falls, WI 1 106
Priest, Edward C Eau Claire, WI 12 547
Rabska, Michael H Eau Claire, WI 1 106
Simmons, Frederick J Neillsville, WI 14 693
Sperry, Christopher J Eau Claire, WI 22 3083

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