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Abstract

A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte width from the main memory in one access, a plurality of vector registers for storing data read by the load pipe, each having a plurality of entries of an 8-byte width, mark bit stacks provided one for each of the vector registers and each having at least the same number of entries as those of the vector register, the entries of each mark bit stack storing mark bits for indicating which one of the plural-byte data stored in the entries of the corresponding vector register is valid, and a shifter for sending the valid data to an operation unit in accordance with the mark stored in the mark bit stack.

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First Claim