High-speed determining unit for prioritizing and arbitrating among competing input signals
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United States of America Patent
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Sep 14, 1993
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app pub date -
Jun 10, 1991
filing date -
Oct 15, 1987
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Abstract
A determining unit in a computer, communication of other system for determining which one of a plurality of requests by competing input signals is to be honored. The determining unit includes a priority and an arbiter unit with a plurality of stages of arbiter blocks cascaded together from arbiter blocks in a first stage to arbiter blocks in a last stage in a binary tree. The forward output signals from blocks in one stage connect as forward input signals to blocks in a next stage and reverse output signals from blocks in one stage connect as reverse input signals to blocks in a previous stage.
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