On-chip pull-up circuit which may be selectively disabled
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United States of America Patent
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Aug 17, 1993
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N/A
app pub date -
Nov 25, 1991
filing date -
Nov 25, 1991
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Abstract
An on-chip pull-up which can be selectively enabled/disabled comprises a pull-up transistor (e.g., an FET) connected between the line to be pulled up/down and a bias voltage (e.g., a positive voltage V.sub.DD or a negative voltage V.sub.SS). The control lead (e.g., gate lead) of the transistor is then made externally accessible. Connecting the control lead to V.sub.DD or V.sub.SS either enables or disables the pull-up depending on the particular transistor.
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