Importance

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Abstract

Synchronizing pulses are separated from a video signal played back from a magnetic tape recording. The individual synchronizing pulses are then inspected in a digital inspection circuit containing two generic array logic (GAL) units and a counter, operating in conjunction with a gate pulse generated from a electrically programmable read-only memory (EPROM) which is controlled by a counter reset by every validated synchronizing pulse. The inspection is in terms of phase and width of the synchronizing pulse. The pulses that pass inspection are utilized for the playback of the video signal, as are also other timing signals generated by the EPROM. The detection of a dropout in the playback demodulator interrupts the provision of inspected synchronizing signals and also prevents false clamping of the final sync separator, but clock pulses driving the counter that addresses the EPROM, together with a reset signal from the EPROM, maintain certain timing signals during the dropout.

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First Claim