Load current monitor for MOS driver
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 15, 1993
Grant Date -
N/A
app pub date -
Sep 3, 1991
filing date -
Sep 3, 1991
priority date (Note) -
In Force
status (Latency Note)
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Abstract
An integrated circuit chip includes a MOS driver transistor and a relatively small MOS current-monitor transistor having their sources connected to a circuit ground point and their gates connected together to a control-voltage conductor. Current through the monitor transistor flows to a DC voltage supply conductor through a field effect transistor. A differential amplifier has one input connected to the drain of the driver transistor and the other input connected to the drain of the monitor transistor. The output of the differential amplifier is connected to the gate of the field effect transistor to force the drain voltage of the monitor transistor to be equal to the drain voltage of the driver transistor. The current flowing through the small monitor transistor has a constant proportionality with the load current even as the load current approaches zero. With the addition of a differential voltage amplifier having an output connected to the control-voltage conductor, having one input connected to a circuit ground point, and the other input connected to a control-current input pad, the current from the monitor transistor is fedback via a current mirror circuit to the other input of the voltage amplifier, so that the entire circuit can be made to perform as a current amplifier, e.g. driver-load-current/input-control current. By connecting one end of an external precision resistor to the control-current-input pad of the chip and applying a control voltage to the opposite end of the precision resistor, a control current proportional to the control voltage is caused to flow through the control-circuit-input pad. The combination performs as a current amplifier.

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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
Patent Owner | Address | |
---|---|---|
ALLEGRO MICROSYSTEMS INC A CORP OF DELAWARE | WORCESTER MA |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Kovalcik, Thomas J | Barrington, NH | 5 | 123 |
Latham, II Paul W | Durham, NH | 17 | 720 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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