Memory arrangement with a read-out circuit for a static memory cell
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United States of America Patent
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Jun 1, 1993
Grant Date -
N/A
app pub date -
Dec 13, 1991
filing date -
Dec 21, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A memory arrangement that includes a static memory cell with two MOSFETs that are connected such that an input signal for setting the memory cell is applied to one MOSFET, and the output of the other MOSFET is connected to the input of the first MOSFET, so that one MOSFET is always conductive while the other is blocked. The two MOSFETs are connected with positive feedback. In each case, the gate electrode is connected to a voltage equal to half the battery voltage. The source electrode of the first (N channel) MOSFET forms the input of the memory cell. The drain electrode of the first MOSFET is connected to the source electrode of the second (P channel) MOSFET. The blocking resistance of the drain-substrate diode of the first MOSFET is greater than the blocking resistance of the source-substrate diode of the second MOSFET. Also, the output voltage of the first (N channel) MOSFET is greater than the sum of the gate voltage and the threshold voltage of the second (P channel) MOSFET.
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