Asynchronous time division switching arrangement and a method of operating same
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United States of America Patent
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May 18, 1993
Grant Date -
N/A
app pub date -
Sep 29, 1989
filing date -
Oct 6, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.
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