Importance

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Abstract

An image having more pixels than can be displayed on a video monitor (16) is stored in an image buffer (10) in packed raster format. During a vertical retrace period, the video monitor generates several horizontal synchronization signals which clock a video memory controller (20). Each time the video memory controller is clocked, it moves a portion of a next successive row of data from the image buffer to a video memory (12). In this manner, several rows of new data are loaded into the video memory before the video monitor starts withdrawing data from the video memory to display the first raster scan line. As the raster scan line is indexed to move down the video image by the horizontal synchronization pulses, the same horizontal synchronization pulses continue to index the row addresses of the video memory controller keeping the transfer of new data into the video memory several lines ahead of the current raster scan line. In a panning mode, the vertical synchronization signal of the video monitor resets the video memory controller to a new initial starting address (26') shifted a small distance, e.g. one pixel from a preceding data transfer start address (26). This causes the next frame which is displayed to be shifted the small amount from the preceding frame. In this manner, the image is panned smoothly without perceivable flicker.

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First Claim