Importance

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Abstract

A FISO analog signal acquisition system includes a plurality of CCD arrays (20a-20d), with each array containing a plurality of CCD serial registers (22). Each serial register (22) has a first cell (23) and a large number of additional cells (24) coupled in series with the first cell (24), with acquired samples being transferred along the string of additional cells (24) according to a clock signal having two or more phases, with each CCD array (20a-20d) operating in response to a set of clock signals having a different phase (P1,P2,/P1,/P2). A tapped delay line (10), or other similar hold signal generating means, produces a plurality of closely spaced-in-time sequential hold signals in response to a master hold signal. In response to each one of the hold signals, a CMOS transistor (Q.sub.x) briefly connects an associated first cell (23) to the signal to be sampled so that a series of closely spaced-in-time samples of the signal are acquired. When all of the first cells (23) in one array (20x) are full, the first cells (23) of the next array (20x+1) begin to fill. While each array (20x+1) is filling, clocks to the preceding array (20x) shift the acquired data one location along the CCD serial shift registers (22). The process of acquiring and shifting data is repeated rapidly across the plurality of arrays (20a-20d) until they are filled. The data is then readout slowly through a parallel-in, serial-out CCD shift register (25) connected across the ends of all of the registers (22) of all of the CCD arrays (20a-20d).

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