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Abstract

A flat pulse generator (FPG) with a short settling time and high and low output levels which are both flat is achieved by using source coupled FET logic (SCFL). GaAs MESFETs may be used due to the wide allowable threshold voltage range of SCFL, thereby allowing very fast operation of the FPG. The FET sources of the SCFLs are commonly connected to a constant current source and are operated in the drain current saturation region so that gate-drain capacitance and hence feed-through capacitance is lowered. The feed-through capacitance is further reduced by cross connecting the SCFLs so that their feedthrough components cancel each other or by connecting small capacitors between the gate and drain of respective FETs. Due to such configurations, the drain voltage can be outputted directly so as to minimize the disturbance of the output wave form due to impedance mismatch.

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