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Abstract

A high performance graphics display system for use as an engineering workstation includes a compact method of generating vectors and transmitting addresses for same from a picture processor to frame buffer control circuitry for writing or reading pixel values along the vector in the frame buffer. The system uses a multiplexed address/data bus. Off-screen memory in communication with the picture processor is used to store pixel data read along vectors in the frame buffer preceding writing a vector so that the original data can be restored when the written vector is moved or removed. Vectors are encoded by the picture processor as a first word containing the address of the beginning point of the vector and major axis and X and Y direction bits to indicate the vector's direction. A second word includes a minor axis bit, indicating whether the next pixel to be written or read is on or off the major axis, in the direction indicated for such axis in the first word. The first word also includes a hesitate bit indicating whether the first pixel of a vector is to be written or read. The system is configured in pipe stages with a FIFO at each stage controlled by a hold signal that is pipelined from downstream stages in a direction opposite the pipelined data flow.

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First Claim