High speed logic circuit
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United States of America Patent
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Jan 19, 1993
Grant Date -
N/A
app pub date -
Aug 8, 1991
filing date -
Aug 8, 1991
priority date (Note) -
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Abstract
An improved GaAs switching device is disclosed, of the type having a switched clamp which shunts pull-up current except during a portion of a '0' to '1' transistion at the device's output. The device herein provided enhanced immunity to interconnect resistance by isolating the gate-to-source Schottky diode of the clamp's FET from the device's output node. In accordance with the invention, the gate-to-source current through the clamp's FET is limited by an impedance device in the FET's gate circuit to provide the isolation.
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