Single event upset hardening circuits, devices and methods
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United States of America Patent
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Dec 29, 1992
Grant Date -
N/A
app pub date -
Feb 5, 1990
filing date -
Feb 5, 1990
priority date (Note) -
Expired
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Abstract
The present invention provides a unique circuit and layout methods for improving upon series redundant circuits. A substitution device, comprising a pair of series connected N or P FETs for respective single FETs, can be further hardened or enhanced against cosmic rays, particles, etc. by spacing the P FETs a predetermined distance apart so that an ion or other particle cannot strike or affect both channels simultaneously, thus avoiding upset. When these devices are placed in cells (i.e., ASIC) in logic or the like circuits, the predetermined spacing is related to cell height. Also, alignment of the gates of the substitution device on a common axis minimizes the window of a satellite through which a particle could effectively strike the common gate axis possibly to upset both gates.
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