Method and apparatus for the inspection of patterns

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United States of America Patent

PATENT NO 5173719
SERIAL NO

07630190

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The present invention relates to a technique, in the inspection of a defect of a semiconductor memory or the like, in which chip comparison is separated from repetitive pattern comparison in a region of a wafer to be inspected whereby both the comparisons are rendered possible to perform in parallel in one and the same scanning.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTDCHIYODA-KU TOKYO
HITACHI TOKYO ELECTRONICS CO LTDOME-SHI TOKYO 198-8532

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fukui, Tooru Hamura, JP 2 43
Hori, Yoshiichi Kodaira, JP 1 39
Kamagata, Takahiro Honmachi, JP 1 39
Saito, Mikihito Tokyo, JP 2 90
Taniguchi, Yuzo Higashimurayama, JP 19 458

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