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Abstract

An improved memory system for use in a data processing system which memory system has two memory banks and corresponding error correction circuitry associated with each. Data words of a block thereof are stored in the memory banks in an interleaved fashion wherein alternating words are stored in one bank and intervening alternating words are stored in the other bank. During a write operation the memory is controlled so that the first data word of a block stored in a memory bank uses a late write technique and all subsequent data words thereof use an early write technique. During a read operation, pairs of data words are read and checked for errors simultaneously and are then supplied in a pipelined manner.

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First Claim