Boot-strapped decoder circuit
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United States of America Patent
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Nov 24, 1992
Grant Date -
N/A
app pub date -
Oct 2, 1990
filing date -
Oct 2, 1990
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A boot-strapped decoder circuit in accordance with the present invention activates a selected word line output in response to an input address. The decoder circuit includes a plurality of row decoders, each of which has a plurality of word line outputs. The row decoders respond to a select signal that identifies one of the row decoders as a selected row decoder. The select signal is generated by a regular predecoder based on the most significant bits of the input address. Low order predecoder circuitry utilizes the least significant bits of the input address to generate a low order decoder signal. The selected row decoder includes boosting means coupled to each of the selected row decoder outputs and responsive to the low order predecode signal for generating a boot-strapped output voltage on a selected word line output of the selected row decoder.
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