Low contact resistance process

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United States of America Patent

PATENT NO 5166095
SERIAL NO

07627680

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Abstract

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A process to reduce M1/N+ contact resistance includes a low temperature anneal step, after the aluminum interconnect is alloyed at 400.degree. C. During the low temperature anneal step, the temperature of the furnace tube is lowered from 400.degree. C. to 250.degree. C. over a period of two hours, after which the integrated circuit is annealed under nitrogen for a further period of one hour. Alternately, the low temperature anneal is performed in an oven filled with nitrogen for a period of two hours at 250.degree. C.

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Patent Owner(s)

Patent OwnerAddress
SAMSUNG SEMICONDUCTOR INC A CORP OF CA3725 NORTH FIRST ST SAN JOSE CA 95134-1708

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hwang, Stephen San Jose, CA 8 362

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