Importance

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Abstract

A memory circuit comprises a memory array having a plurality of memory cells arranged in rows and columns. Column select circuits enable access to the columns in the array. Each column select circuit is associated with a respective group of the columns and is arranged to access a selected one of the columns in the respective group. At least one spare memory column is provided. Also included are a plurality of read/write circuits associated respectively with the groups, and with the spare memory column, for reading or writing data bits between a data bus and the columns selected by the column selected circuits. Routing circuitry is connected between the read/write circuits and the data bus and is programmable with information identifying at least one faulty column. The routing circuitry is operable in response to an attempted access to the faulty column by disconnecting from the data bus the read/write circuit associated with the group containing the faulty column and connecting to the data bus the read/write circuit associated with the spare column thereby to transfer data between the spare column and the data bus.

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First Claim