Circuit for dynamic isolation of integrated circuits
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United States of America Patent
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Oct 27, 1992
Grant Date -
N/A
app pub date -
Nov 28, 1990
filing date -
Nov 29, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A dynamic isolation circuit belonging to a monolithic integrated circuit comprising lateral transistors and vertical transistors. The lateral transistors are isolated by an isolating region connected to an isolating potential (V.sub.iso), these lateral transistors being connected up to voltages of a first polarity relative to a reference voltage (GND), the power terminal connected up to the rear face normally being at a potential (V.sub.out) of the first polarity relative to the reference voltage. This circuit comprises a sign-detector (D) for detecting the sign of the potential of the rear face relative to the reference voltage, at least one lateral transistor (S1) to connect the isolating potential to the reference potential when the potential of the rear face is of the first polarity relative to the reference potential, and at least one vertical transistor (S2) to connect the isolating potential to the potential of the rear face when the potential of the rear face is of the second polarity relative to the reference potential.
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