Multi-purpose cache memory selectively addressable either as a boot memory or as a cache memory
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United States of America Patent
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Oct 13, 1992
Grant Date -
N/A
app pub date -
May 11, 1987
filing date -
May 11, 1987
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a master-slave multiprocessor (FIG. 1), a slave processor (110) includes a random access memory array (119) that serves at initialization time as the slave processor's boot memory and that serves during normal operation time as the slave processor's cache memory. A master processor (120) writes the slave processor's boot program into the memory array when the memory array is to serve as the boot memory, i.e., following system reset.
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