Apparatus for a dual thickness floating gate memory cell

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United States of America Patent

PATENT NO 5153691
SERIAL NO

07746170

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Abstract

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A semiconductor integrated circuit device is disclosed having first and second conducting layers, with the first layer having a shape which enhances field emission tunneling off of the surface thereof. A dual thickness dielectric layer separates the conducting layers. When a potential difference is applied between the conducting layers, field emission tunneling occurs primarily through the thinner portion of the dielectric layer. A method for forming a semiconductor integrated circuit device comprises the steps of (a) forming a first conducting layer, (b) forming regions of enhanced field emission on said first conducting layer, (c) forming a second insulating layer on the first conducting layer, (d) forming a masking layer (e) undercutting the second insulating layer, (f) etching the first conducting layer according to the masking pattern, (g) forming a third insulating layer on all exposed surfaces of the first conducting layer, such that a resultant insulating layer has first and second regions of different thicknesses, and (h) forming a second conducting layer over said resultant insulating layer.

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Patent Owner(s)

Patent OwnerAddress
XICOR LLC1650 ROBERT J CONLAN BLVD NE MS 62A-309 PALM BAY FL 32905

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Guterman, Daniel C Fremont, CA 166 13852

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