Floating-point ALU with parallel paths
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United States of America Patent
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Aug 4, 1992
Grant Date -
N/A
app pub date -
May 4, 1990
filing date -
May 4, 1990
priority date (Note) -
Expired
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Abstract
A method and apparatus for improving the speed of a floating-point arithmetic logic unit (ALU) by arranging the logic to provide two parallel paths, each performing four functions. Six different functions are performed, and thus there is a duplication of two functions. However, each path requires only four functions, thus reducing the throughput from six to four functions. Logic circuitry is provided to determine whether the exponents of the operands are close or not, and thus select one or the other of the two paths. The fractions of the operand are processed on the two paths in parallel while the logic is determining which path to select. This determination can thus be done in parallel, with the selection being done by a multiplexer at the end of the two parallel paths.
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