Closed cell transistor with built-in voltage clamp

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United States of America Patent

PATENT NO 5136349
SERIAL NO

07597118

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Abstract

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A power transistor takes advantage of the lower breakdown voltage capability of a spherical junction. A clamping region having a spherical shape is provided in the gater region of an enclosed transistor cell. The clamping region has a lower breakdown voltage than do the active portions of the transistor cell. Both a DMOSFET and an IGBT transistor may be provided with the clamping region. The clamping region is a zener diode in the case of the DMOSFET, and is a bipolar junction transistor in the case of the insulated gate bipolar transistor. The clamping region is preferably an island in the center of each cell of a closed cell structure.

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Patent Owner(s)

Patent OwnerAddress
SILICONIX INCORPORATED2585 JUNCTION AVENUE SAN JOSE CALIFORNIA 95134-1923 95134-1923

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bencuya, Izak San Jose, CA 34 1532
Yilmaz, Hamza Sunnyvale, CA 292 5131

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