Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
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United States of America Patent
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Jul 21, 1992
Grant Date -
N/A
app pub date -
Mar 23, 1990
filing date -
Mar 23, 1990
priority date (Note) -
Expired
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Abstract
Transistor structure using a lightly doped drain (LDD) technique are disclosed. The present invention provides a reduced on-resistance in the LDD region, while retaining substantially all the high breakdown voltage advantage of the LDD technique. The advantage of the present invention is achieved by applying a non-uniform impurity design in the LDD region, increasing gradually from the gate-edge towards the contact.
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