Beam synchronized coprocessor
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United States of America Patent
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-
Apr 7, 1992
Issued Date -
N/A
app pub date -
Oct 16, 1989
filing date -
Jul 18, 1986
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
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