Method of making buried stacked transistor-capacitor
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United States of America Patent
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-
Mar 31, 1992
Grant Date -
N/A
app pub date -
Feb 29, 1988
filing date -
Feb 29, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A buried interconnected transistor and capacitor are formed in a trench etched in a semiconductor wafer having a lightly doped surface layer. The trench extends through the surface layer into the substrate. A dielectric liner is provided in the trench and the trench partially refilled with polysilicon up to the surface layer. The dielectric liner is removed thereby exposing sidewalls of the surface layer in the trench. Further silicon is deposited which forms additional poly material on the poly plug, single crystal material on the exposed epi-sidewalls, and further poly above the single crystal material. A dielectric is formed over the deposited material and a gate electrode deposited over the single crystal portion on the sidewall. The poly plug serves as one plate of a buried trench capacitor and the single crystal material accommodates the channel of the series MOSFET connected to the poly plug capacitor plate.
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