Method for manufacture of an integrated MOS semiconductor array
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United States of America Patent
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Mar 10, 1992
Grant Date -
N/A
app pub date -
Oct 9, 1990
filing date -
Oct 11, 1989
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of manufacture of an integrated MOS semiconductor array for the low-frequency range having MOS components and circuit paths arranged on a semiconductor substrate. Exposed surfaces between the circuit paths are made hydrophobic by germinating with hexamethyl disilazane ((CH.sub.3).sub.3 SiNHSi(CH.sub.3).sub.3), so that the occurrence of leakage currents is avoided. In addition, in an integrated MOS semiconductor array in which the MOS components and the circuit path are covered with a protective layer, the surface of this protective layer is made hydrophobic. As a result, both leakage currents and parasitic capacitances are prevented.
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- 6 Citation Count
- H01L Class
- 0 % this patent is cited more than
- 33 Age