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Abstract

A low distortion capacitor sampling circuit includes a sampling MOSFET, the source electrode of which receives a time-varying input voltage to be sampled. A bootstrap capacitor has a first terminal connected to the gate electrode of the sampling MOSFET and to a first MOSFET that charges the first terminal of the bootstrap capacitor to a first voltage in response to a first control signal. A delayed second control signal is applied to the gate of a second MOSFET the drain electrode of which is connected to a second terminal of the bootstrap capacitor to keep the pulldown MOSFET on until the charging of the sampling capacitor is complete. Then a third control signal turns on a third MOSFET, boosting both terminals of the bootstrap capacitor. The second control signal then turns the third MOSFET off, electrically isolating the gate electrode of the sampling MOSFET. Changes in the time-varying input voltage are coupled by the gate-to-source capacitance of the sampling MOSFET to the gate electrode thereof. The input voltage is simultaneously applied to a source follower circuit, the output of which is coupled by a CMOS transmission gate to the body electrode of the sampling MOSFET. The circuit avoids harmonic distortion due to modulation of channel resistance of the sampling MOSFET by keeping the gate-to-source voltage and the source-to-body electrode voltage independent of the input voltage.

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