Importance

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Abstract

A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated. If the transfer complete signal is not generated, a transfer inhibits signal is generated for inhibiting the generation of the succeeding DATA-ACC signal and hence the next CPU-XFR signal.

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First Claim