Device for addressing of redundant elements of an integrated circuit memory
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United States of America Patent
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Oct 15, 1991
Issued Date -
N/A
app pub date -
Jan 17, 1990
filing date -
Mar 3, 1987
priority date (Note) -
Expired
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Abstract
A device for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, and at least one group of fuses to store the address of a faulty element of the memory. Each fuse is associated with a row/column address pair. Through the blowing of certain fuses in the group after testing of a memory element, the address either of a column element, if the faulty element is a column element, or of a row element, if the faulty element is a row element, is stored. Only the row addresses are enabled when the stored address is that of a row element, and only the column addresses are enabled when the stored address is that of a column element, in order to address either a row redundant element or a column redundant element.
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