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Abstract

A variable word length (VWL) decoder is disclosed in which an input bit stream of variable length words is input to a programmable logic array (PLA) (305) through an input shift register (302). The data association input plane (306) of the PLA compares the sequence of input bits in the register with all the possible variable length words. When a match is made, the PLA's length output plan (307) produces an output word representing the length of the detected variable length word and the PLA's word output plan (308) produces the fixed length word corresponding to the input VWL word. This fixed length word is input to a latch which is controlled by a downcounter (311). The length word is loaded into this downcounter, which decrements its count as the input bits are shifted through the register. Only when its count reaches zero have all bits of the previous variable length word been clocked through the shift register. Therefore, only on the count of zero does the output of the word output plane represent a fixed length word that properly corresponds to a valid VWL input word. Thus, only on the count of zero is the latch enabled to transfer to its output the word then at the output of the word output plane. The feedforward only architecture of the VWL decoder does not require any information regarding the decoded word length to be fed back to the input. This architecture is therfore not limited by speed constraints that would otherwise exist if the length of each decoded word needed to be fed back to the input before the next word could be decoded.

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