Multiplier-adder in the Galois fields, and its use in a digital signal processing processor
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United States of America Patent
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Sep 3, 1991
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N/A
app pub date -
Nov 3, 1989
filing date -
Mar 17, 1988
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Expired
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Abstract
The multiplier-adder in the Galois fields can have parameters applied to it, i.e. it is possible to choose the Galois field CG(2.sup.m) in which the polynomial operations are performed, with m at most equal to N, N being predetermined by the designer. The multiplier-adder is made up of a decoder (10) organized as N identical elementary cells receiving the generator polynomial G(m:0) and supplying the generator polynomial without its least significant bit G(m-1:0) and a polynomial marking the degree of the generator polynomial, DG(m-1:0), and a computing matrix (20) organized as N columns of identical elementary cells receiving the polynomials A, B and C of the Galois field CG(2.sup.m) and supplying a polynomial result P=(A*B).sub.modulo G +C. The multiplier-adder has usage for example as a digital signal processing processors for error detecting and correcting encoding and decoding using BCH or RS codes.
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