Slip phase control PLL
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United States of America Patent
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Sep 3, 1991
Grant Date -
N/A
app pub date -
Feb 21, 1990
filing date -
Oct 19, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A slip phase control phase-locked loop includes a voltage-controlled oscillator for generating a frequency signal, and a binary programmable frequency divider for producing a frequency-divided signal in response to the frequency signal supplied thereto, the binary programmable frequency divider including a 2-scale-factor prescaler, a swallow counter, and a main counter. The phase of the frequency-divided signal is compared with the phase of a reference frequency signal. A phase-compared signal is integrated and the integrated signal is applied to the voltage-controlled oscillator. A D/A converter swallow counter and a D/A converter counter are operable with the binary programmable frequency divider for D/A-converting a signal derived from the frequency signal into a pulse-width-modulated signal corresponding to the phase-compared signal at a present count ranging from 0 to 2.sup.M -1, where M is a positive integer.
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