Programmable logic array with reduced power consumption
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United States of America Patent
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Jul 16, 1991
Grant Date -
N/A
app pub date -
Apr 6, 1989
filing date -
Apr 11, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A programmable logic array includes a programmable logic array being precharged and discharged in synchronism with a clock signal supplied thereto and outputting an operation result with respect to input data supplied thereto. The programmable logic array also includes a circuit connected to the programmable logic array, for holding the programmable logic array in a precharged state by setting the clock signal to a fixed level when the programmable logic array is not selected and for switching the programmable logic array to a discharged state by supplying the clock signal the programmable logic array when the programmable logic array is selected, so that the programmable logic array is discharged on the basis of the contents of the input data when selected.
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