Device for timing interrupt acknowledge cycles
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United States of America Patent
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Jul 16, 1991
Issued Date -
N/A
app pub date -
May 7, 1990
filing date -
May 18, 1988
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A peripheral device containing a control circuit with internal timing which enables it to independently adjust the timing of an interrupt acknowledge cycle. The circuit senses a timing signal from the CPU and asserts a control signal to suspend the operation of the CPU for a predetermined period of time. The predetermined period of time is customized to the peripheral so that when the CPU is re-activated and reads from the bus, a valid interrupt vector will have been put out by the peripheral.
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