Output circuit having high charge to voltage conversion gain
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United States of America Patent
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Jul 2, 1991
Grant Date -
N/A
app pub date -
Apr 2, 1990
filing date -
Mar 31, 1989
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An output circuit for CCD imager devices or CCD delay devices is disclosed in which a depletion type second MIS transistor is connected to the drain side of a first MIS transistor constituting a source follower adapted for converting transferred signal signals into an electrical voltage, and an output voltage is supplied to the gate of the second MIS transistor. This depletion type second MIS transistor causes the drain potential of the first MIS transistor to be changed in phase with the input electrical charges to reduce the gate-to-drain capacitance of the first MIS transistor to improve the charge-to-voltage conversion gain.
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