High-speed bipolar memory system
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United States of America Patent
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Jul 2, 1991
Issued Date -
N/A
app pub date -
Jan 22, 1990
filing date -
Jan 11, 1988
priority date (Note) -
Expired
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Abstract
A switched load diode cell has been developed wherein first and second multi-emitter NPN transistors are provided having bases cross coupled to the other's collectors in typical latch fashion as shown in FIG. 5. A PN diode is provided having an anode coupled to the select line through a load resistor and a cathode coupled to the collector of each associated multi-emitter transistor. A parasitic lateral PNP transistor associated with the PN diode is provided having an emitter coupled to the select line through the same load resistor and a collector connected to the base of the associated multi-emitter transistor. A relatively low resistance load of about 500.OMEGA. is connected between the common node which consists of the emitter of the parasitic lateral PNP transistor and the anode of the PN diode and the select line. In this way, a switched load diode cell is provided. Parasitic PNP beta rolls off heavily with current, and the parasitic PNP transistor is nothing more than a PN diode if the beta of the PNP (beta.sub.P) is approximately 0. Therefore, the beta.sub.P is to be very low at high current (sense current), and the beta product (beta.sub.P .times.beta.sub.N) is to be less than 1. In the standby mode, with only standby current flowing in either emitter, beta.sub.P .times.beta.sub.NSTBY is much more than 1. Therefore, with low standby current, the cell acts just like a PNP loaded cell. But when the cell is being sensed, the cell effectively becomes a resistor with diode loaded cell. A multi-emitter transistor is therefore provided wherein the emitters can have different betas, the betas being achieved by providing a thicker base width and/or higher doping and thereby a lower beta for the reading emitter, and a thinner base width and/or lower doping, and therefore a higher beta for the standby emitter. The change can be achieved by implanting locally into the region defining the base for the outer or read emitter. Using this high/low beta approach, the implementation of the beta product requirement became much easier.

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Patent Owner(s)
Patent Owner | Address | |
---|---|---|
MICEL INCORORATED | 1849 FORTUNE DRIVE SAN JOSE CA 95131 |
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Wai, Wong Thomas S | San Jose, CA | 1 | 11 |
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Maintenance Fees
Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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