Programmable - voltage - generator interface for decreasing the minimum voltage step
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United States of America Patent
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Jun 11, 1991
Issued Date -
N/A
app pub date -
Mar 15, 1989
filing date -
May 28, 1985
priority date (Note) -
Expired
status (Latency Note)
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Abstract
An interface circuit to the output of a programmable voltage ramp generator for decreasing the minimum voltage step of such a generator having two voltage channels and a minimum voltage step greater than 1 millivolt. The interface circuit receives an input from each of the two voltage channels (V.sub.2, V.sub.3), along with an inserted voltage (V.sub.1). The circuit includes a summing amplifier for (i) compressing the minimum voltage step from one voltage channel (V.sub.2) by a factor equal to or greater than such minimum voltage step, (ii) adding the voltage from the other channel (V.sub.3) to the compressed voltage, and (iii) subtracting the inserted voltage (V.sub.1) (or adding an inserted voltage which is negative). The inserted voltage (V.sub.1) is equal in magnitude to the maximum output value from the voltage channel that has the voltage compressed (V.sub.2). The output of the summing amplifier (V.sub.out) may be represented by: V.sub.out =(V.sub.3 /X)+(V.sub.2 /Y)+(V.sub.1 /Z) where X, Y, Z=attenuation or amplication factors. The interface circuit decreases the minimum voltage step at channel V.sub.2 by a factor Y down to a minimum voltage step of 1 millivolt or less.
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